US 12,424,272 B2
Method for adjusting logic states of data strobe signals used by memory device
Wu-Der Yang, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Nov. 23, 2023, as Appl. No. 18/518,549.
Application 18/518,549 is a division of application No. 18/379,819, filed on Oct. 13, 2023.
Prior Publication US 2025/0124973 A1, Apr. 17, 2025
Int. Cl. G11C 7/10 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4076 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A control unit of a memory, comprising:
a first input stage comprising a first input terminal configured to receive a first signal and a second input terminal configured to receive a second signal; and
a first output stage connected to the first input stage and comprising an output terminal configured to generate a first processed signal;
a second input stage comprising a first input terminal configured to receive the second signal and a second input terminal configured to receive the first signal;
wherein, if the first signal and the second signal are identical, the first input stage is open-circuit to separate the first processed signal from the first signal;
wherein the first output stage comprises a first resistor having a first resistance and the first input stage has a second resistance greater than the first resistance.