US 12,424,271 B2
Semiconductor apparatus and semiconductor system having lun selection cycle, and operating method of semiconductor system
Jae Young Lee, Icheon-si (KR); and Won Sun Park, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Apr. 7, 2023, as Appl. No. 18/297,375.
Claims priority of provisional application 63/328,521, filed on Apr. 7, 2022.
Claims priority of application No. 10-2023-0031254 (KR), filed on Mar. 9, 2023.
Prior Publication US 2023/0326517 A1, Oct. 12, 2023
Int. Cl. G06F 12/02 (2006.01); G06F 13/20 (2006.01); G11C 7/10 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4096 (2013.01) [G06F 13/20 (2013.01); G11C 7/1048 (2013.01); G11C 7/1096 (2013.01); G11C 11/4093 (2013.01); G06F 2213/40 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor system comprising:
a first semiconductor apparatus configured to provide a command signal and an address signal, to transmit the command signal during a command cycle, to transmit the address signal during an address cycle, and to transmit a selection signal during a logical unit number (LUN) selection cycle before the command cycle; and
a second semiconductor apparatus including a first die and a second die, each of the first and second dies being configured to perform a data input/output operation based on the selection signal, the command signal, and the address signal,
wherein each of the first and second dies includes a memory cell array including a plurality of planes, and the selection signal includes information for selecting one of the first and second dies and information for selecting at least one of a plurality of planes of a selected die.