US 12,424,270 B2
Semiconductor memory device and memory module having various operation modes
Gunhee Cho, Suwon-si (KR); and Wonyoung Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 11, 2023, as Appl. No. 18/315,571.
Claims priority of application No. 10-2022-0118840 (KR), filed on Sep. 20, 2022.
Prior Publication US 2024/0096404 A1, Mar. 21, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); G11C 29/50 (2006.01)
CPC G11C 11/4093 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4087 (2013.01); G11C 11/4096 (2013.01); G11C 29/50012 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a receiving circuit configured to receive a plurality of input command/address (CA) signals, and to generate a plurality of CA signal groups based on the input CA signals and a clock signal, each of the plurality of CA signal groups including a first sub-signal representing a command and a second sub-signal representing an address associated with the command;
a multiplexing circuit configured to output each of the plurality of CA signal groups as a corresponding selected CA signal group in a first operation mode, and output a plurality of selected CA signal groups by combining at least two of the CA signal groups into a single selected CA signal group in a second operation mode;
a decoding circuit configured to generate a plurality of output CA signals based on the plurality of selected CA signal groups; and
a memory cell array configured to operate based on the plurality of output CA signals.