US 12,424,269 B2
Semiconductor memory device capable of adaptively controlling bias and method of operating the same
Sun Young Kim, Suwon-si (KR); Sang-Yun Kim, Suwon-si (KR); and Younghun Seo, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 18, 2023, as Appl. No. 18/199,114.
Claims priority of application No. 10-2022-0118854 (KR), filed on Sep. 20, 2022.
Prior Publication US 2024/0096401 A1, Mar. 21, 2024
Int. Cl. G11C 5/02 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); H10B 12/00 (2023.01)
CPC G11C 11/4091 (2013.01) [G11C 11/4085 (2013.01); H10B 12/50 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory cell area including a plurality of memory cells, each of which includes a first transistor to which a first back bias voltage is applied and a capacitor connected to the first transistor and in which data is stored; and
a peripheral circuit area which overlaps the memory cell area in a first direction and includes a plurality of second transistors to which a second back bias voltage controlled differently from the first back bias voltage is applied,
wherein the second back bias voltage is different from the first back bias voltage, and
wherein the second back bias voltage is applied to the plurality of second transistors in response to a temperature change of the semiconductor memory device.