US 12,424,263 B2
Apparatuses and methods for arranging read data for output
Ryo Fujimaki, Sagamihara (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on May 27, 2022, as Appl. No. 17/827,582.
Prior Publication US 2023/0386556 A1, Nov. 30, 2023
Int. Cl. G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4076 (2013.01) [G11C 11/4093 (2013.01); G11C 11/4096 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a clock circuit configured to provide multiphase clock signals having different phases from each other based on a clock signal;
a data output circuit configured to receive the multiphase clock signals and a plurality of read data bits responsive to a read command, the data output circuit comprising:
a data register configured to receive the multiphase clock signals and the plurality of read data bits, the plurality of read data bits clocked into the data register in parallel based on the multiphase clock signals; and
a serializer circuit configured to receive the plurality of read data bits from the data register in parallel and further receive the multiphase clock signals, each of the plurality of read data bits output serially from the serializer circuit in synchronism with a corresponding one of the multiphase clock signals; and
a control circuit configured to determine the correspondences between the plurality of read data bits and the multiphase clock signals based on information about which of the multiphase clock signals captures the read command.