US 12,424,262 B2
Voltage supply structure for memory cell capable of securing area margin, semiconductor apparatus including the same, and operating method of the semiconductor apparatus
Eun Gu Han, Icheon (KR)
Assigned to SK hynix Inc., Icheon (KR)
Filed by SK hynix Inc., Icheon (KR)
Filed on Jun. 14, 2023, as Appl. No. 18/334,962.
Claims priority of application No. 10-2023-0000659 (KR), filed on Jan. 3, 2023.
Prior Publication US 2024/0221816 A1, Jul. 4, 2024
Int. Cl. G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01)
CPC G11C 11/4074 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4094 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A voltage supply structure, comprising:
a first global switch that connects a global positive line and a local positive line in response to a first common address signal;
a first local column switch that connects the local positive line and a bit line in response to a first local column address signal;
a first local row switch that connects the local positive line and a word line in response to a first local row address signal; and
a memory cell connected between the bit line and the word line.