US 12,424,256 B2
Circuit design and layout with high embedded memory density
Fa-Shen Jiang, Taoyuan (TW); Hsia-Wei Chen, Taipei (TW); Hsun-Chung Kuang, Hsinchu (TW); Hai-Dang Trinh, Hsinchu (TW); and Cheng-Yuan Tsai, Chu-Pei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 28, 2024, as Appl. No. 18/589,540.
Application 18/589,540 is a continuation of application No. 18/076,801, filed on Dec. 7, 2022, granted, now 11,961,545.
Application 18/076,801 is a continuation of application No. 17/379,025, filed on Jul. 19, 2021, granted, now 11,545,202, issued on Jan. 3, 2023.
Claims priority of provisional application 63/182,022, filed on Apr. 30, 2021.
Prior Publication US 2024/0203472 A1, Jun. 20, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/16 (2006.01); G11C 11/56 (2006.01); H10B 53/30 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01)
CPC G11C 11/161 (2013.01) [G11C 11/1657 (2013.01); G11C 11/1659 (2013.01); G11C 11/5614 (2013.01); G11C 11/5657 (2013.01); G11C 11/5678 (2013.01); H10B 53/30 (2023.02); H10B 61/22 (2023.02); H10B 63/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a transistor over a substrate and comprising a first source/drain region and a second source/drain region;
a first memory cell electrically coupled to the first source/drain region and overlying and spaced from the first source/drain region; and
a second memory cell electrically coupled to the second source/drain region and overlying and spaced from the second source/drain region.