US 12,424,177 B2
Display device and electronic device
Atsushi Umezaki, Kanagawa (JP); and Hajime Kimura, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Sep. 16, 2024, as Appl. No. 18/885,890.
Application 18/885,890 is a continuation of application No. 18/370,427, filed on Sep. 20, 2023, granted, now 12,100,368.
Application 18/370,427 is a continuation of application No. 17/943,284, filed on Sep. 13, 2022, granted, now 11,769,462, issued on Sep. 26, 2023.
Application 17/943,284 is a continuation of application No. 17/460,497, filed on Aug. 30, 2021, granted, now 11,455,969, issued on Sep. 27, 2022.
Application 17/460,497 is a continuation of application No. 16/785,710, filed on Feb. 10, 2020, granted, now 11,170,728, issued on Nov. 9, 2021.
Application 16/785,710 is a continuation of application No. 16/199,336, filed on Nov. 26, 2018, granted, now 10,586,505, issued on Mar. 10, 2020.
Application 16/199,336 is a continuation of application No. 15/147,086, filed on May 5, 2016, granted, now 10,153,303, issued on Dec. 11, 2018.
Application 15/147,086 is a continuation of application No. 14/070,700, filed on Nov. 4, 2013, granted, now 9,337,191, issued on May 10, 2016.
Application 14/070,700 is a continuation of application No. 13/026,863, filed on Feb. 14, 2011, granted, now 8,605,073, issued on Dec. 10, 2013.
Claims priority of application No. 2010-033669 (JP), filed on Feb. 18, 2010.
Prior Publication US 2025/0014534 A1, Jan. 9, 2025
Int. Cl. G09G 3/3266 (2016.01); G02F 1/133 (2006.01); G02F 1/1362 (2006.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01); H10D 30/67 (2025.01); H10D 64/27 (2025.01); H10D 84/83 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC G09G 3/3266 (2013.01) [G02F 1/13306 (2013.01); G02F 1/136286 (2013.01); G09G 3/3648 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); G11C 19/287 (2013.01); H10D 30/6755 (2025.01); H10D 64/512 (2025.01); H10D 84/83 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01); G09G 2310/0286 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/08 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to a clock signal line,
wherein one of a source and a drain of the second transistor is electrically connected to the gate signal line,
wherein one of a source and a drain of the third transistor is electrically connected to an output signal line,
wherein the other of the source and the drain of the third transistor is electrically connected to the clock signal line,
wherein a gate of the third transistor is electrically connected to a gate of the first transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the output signal line,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a power supply line,
wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the power supply line,
wherein a gate of the fifth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the power supply line,
wherein a gate of the seventh transistor is electrically connected to a first signal line,
wherein one of a source and a drain of the eighth transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the ninth transistor is electrically connected to the power supply line,
wherein a gate of the ninth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the tenth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the tenth transistor is electrically connected to a gate of the eighth transistor,
wherein a gate of the tenth transistor is electrically connected to the first wiring,
wherein one of a source and a drain of the eleventh transistor is electrically connected to the gate of the eighth transistor,
wherein the other of the source and the drain of the eleventh transistor is electrically connected to the power supply line,
wherein a gate of the eleventh transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the twelfth transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the twelfth transistor is electrically connected to the power supply line, and
wherein a gate of the twelfth transistor is electrically connected to a second signal line.