US 12,424,161 B2
Driving circuit, driving method and display device
Ziyang Yu, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/912,629
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Nov. 9, 2021, PCT No. PCT/CN2021/129599
§ 371(c)(1), (2) Date Sep. 19, 2022,
PCT Pub. No. WO2022/193685, PCT Pub. Date Sep. 22, 2022.
Claims priority of application No. 202110275825.4 (CN), filed on Mar. 15, 2021.
Prior Publication US 2024/0203339 A1, Jun. 20, 2024
Int. Cl. G09G 3/3225 (2016.01)
CPC G09G 3/3225 (2013.01) [G09G 2300/0842 (2013.01); G09G 2310/0243 (2013.01); G09G 2310/0264 (2013.01); G09G 2310/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A driving circuit, comprising a first control circuit, a second control circuit, an energy storage circuit, a first output circuit and a second output circuit, wherein
a first end of the energy storage circuit is electrically coupled to a first node, a second end of the energy storage circuit is electrically coupled to an output driving signal end, and the energy storage circuit is configured to store electric energy;
the first control circuit is electrically coupled to an input driving signal end and the first node, and configured to control a potential at the first node in accordance with an input driving signal from the input driving signal end;
the second control circuit is electrically coupled to a control clock signal end, a first voltage end and the first node, and configured to control the first node to be electrically coupled to the first voltage end under the control of a control clock signal from the control clock signal end;
the first output circuit is electrically coupled to the first node, a first clock signal end and the output driving signal end, and configured to control the output driving signal end to be electrically coupled to the first clock signal end under the control of the potential at the first node; and
the second output circuit is electrically coupled to the first clock signal end and the output driving signal end, and configured to control the output driving signal end to provide an output driving signal in accordance with a first clock signal from the first clock signal end.