US 12,424,154 B2
Display panel and display device
Wenjun Dai, Shanghai (CN); Liang Xing, Shanghai (CN); and Tianyi Wu, Shanghai (CN)
Assigned to Hubei Yangtze Industrial Innovation Center Of Advanced Display Co., Ltd., Wuhan (CN)
Filed by Hubei Yangtze Industrial Innovation Center Of Advanced Display Co., Ltd., Wuhan (CN)
Filed on Jun. 6, 2024, as Appl. No. 18/735,300.
Application 18/735,300 is a continuation of application No. 17/968,266, filed on Oct. 18, 2022, granted, now 12,014,672.
Application 17/968,266 is a continuation of application No. 17/445,182, filed on Aug. 16, 2021, granted, now 11,514,845, issued on Nov. 29, 2022.
Claims priority of application No. 202110490929.7 (CN), filed on May 6, 2021.
Prior Publication US 2024/0321191 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/32 (2016.01); G02F 1/1362 (2006.01)
CPC G09G 3/32 (2013.01) [G02F 1/136204 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0291 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A display panel, comprising a display area;
wherein the display panel further comprises:
a light-emitting element, wherein the light-emitting element is located in the display area;
a pixel circuit, wherein the pixel circuit is located in the display area and the pixel circuit is configured to drive the light-emitting element;
a driver circuit, wherein the driver circuit is located in the display area and the driver circuit is configured to provide a drive signal to the pixel circuit; and
pixel circuit rows, wherein at least one of the pixel circuit rows comprises a plurality of pixel circuits arranged along a first direction, the pixel circuit rows are arranged along a second direction, the first direction and the second direction intersect;
wherein the driver circuit comprises a plurality of stages of shift register circuits cascaded, and at least one stage of shift register circuit is located between adjacent pixel circuit rows;
the shift register circuits comprise odd-numbered stages of shift register circuits and even-numbered stages of shift register circuits;
the odd-numbered stages of shift register circuits are arranged along the second direction, and the even-numbered stages of shift register circuits are arranged along the second direction; and
the odd-numbered stages of shift register circuits and the even-numbered stages of shift register circuits are arranged along the first direction;
wherein the shift register circuit at least comprises a latch module and a buffer module;
along the first direction, the latch module of an odd-numbered stage of shift register circuit is located on a side of the buffer module facing an even-numbered stage of shift register circuit, and the latch module of the even-numbered stage of shift register circuit is located on a side of the buffer module facing the odd-numbered stage of shift register circuit.