US 12,424,143 B2
Shifting register with fewer transistors, driving method, gate driving circuit and display device
Haigang Qing, Beijing (CN); Ming Hu, Beljing (CN); and Haijun Qiu, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Apr. 30, 2024, as Appl. No. 18/650,484.
Application 18/650,484 is a continuation of application No. PCT/CN2023/070183, filed on Jan. 3, 2023.
Prior Publication US 2024/0282238 A1, Aug. 22, 2024
Int. Cl. G09G 3/32 (2016.01); G09G 3/20 (2006.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/2092 (2013.01) [G09G 3/20 (2013.01); G09G 3/3266 (2013.01); G09G 2310/0286 (2013.01); G11C 19/28 (2013.01); G11C 19/287 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A shifting register, comprising:
an input sub-circuit, coupled to a signal input terminal, a first clock signal terminal and a first node; wherein the input sub-circuit is configured to charge and reset the first node under control of the first clock signal terminal;
a control sub-circuit, coupled to the first clock signal terminal, a second clock signal terminal, the signal input terminal, a first power terminal, a second power terminal and a second node; wherein the control sub-circuit is configured to determine a potential of the second node by the first power terminal or the second power terminal under control of the first clock signal terminal, the second clock signal terminal and the signal input terminal; and
an output sub-circuit, coupled to the first power terminal, the second power terminal, the first node, the second node and a signal output terminal; wherein the output sub-circuit is configured to determine a potential of the signal output terminal by the first power terminal or the second power terminal under control of the first node and the second node;
wherein the control sub-circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor;
a gate of the first transistor is coupled to the second clock signal terminal, a first electrode of the first transistor is directly coupled to the second power terminal, and a second electrode of the first transistor is coupled to a first electrode of the second transistor;
a second electrode of the second transistor is coupled to a gate of the third transistor, and a gate of the second transistor is directly coupled to the signal input terminal;
a first electrode of the third transistor is coupled to the second clock signal terminal, and a second electrode of the third transistor is coupled to a first electrode of the fourth transistor; and
a gate of the fourth transistor is coupled to the second clock signal terminal.