| CPC G06T 7/001 (2013.01) [G06T 7/50 (2017.01); G06T 2207/30148 (2013.01)] | 20 Claims |

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1. A computerized system of examining a semiconductor specimen comprising a first layer and a second layer, the system comprising a processing and memory circuitry (PMC) configured to:
obtain a recipe generated during recipe setup based on a reference image of the semiconductor specimen, the reference image having one or more first reference polygons representative of a first structure on the first layer and one or more second reference polygons representative of a second structure on the second layer annotated thereon, the recipe comprising: a template image for each reference polygon of the first and second reference polygons extracted from the reference image, and a template mask associated with the template image and indicative of proximity of a set of locations in the template image to an edge of the reference polygon;
obtain an inspection image of the semiconductor specimen in runtime;
identify one or more first locations of one or more first inspection polygons in the inspection image corresponding to the one or more first reference polygons using template images of the first reference polygons and template masks associated therewith;
determine a first shift for the first layer based on the one or more first locations, and register the first reference polygons with the inspection image based on the first shift;
identify one or more second locations of one or more second inspection polygons in the inspection image corresponding to the one or more second reference polygons using template images of the second reference polygons and template masks associated therewith; and
determine a second shift for the second layer based on the one or more second locations, and register the second reference polygons with the inspection image based on the second shift.
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