| CPC G06K 7/0166 (2013.01) [G06K 7/0008 (2013.01)] | 19 Claims |
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1. A reception circuit of a smart card, comprising:
a first circuit configured to:
receive a wireless signal comprising a plurality of pauses; and
restore the wireless signal to a clock signal; and
a second circuit configured to:
charge a voltage of a first node based on a first logic level of the clock signal;
compare the voltage of the first node with a reference voltage of a first level; and
output, based on the comparison of the voltage of the first node, a synchronization signal indicating a rising starting time point of a last pause of the plurality of pauses of the wireless signal, the last pause corresponding to an end bit of the wireless signal,
wherein the synchronization signal transitions from a first logic level to a second logic level at the rising starting time point of the last pause of the plurality of pauses and maintains the second logic level at rising starting time points of remaining pauses of the plurality of pauses.
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