| CPC G06F 30/398 (2020.01) [G06F 30/392 (2020.01); H10B 43/50 (2023.02)] | 20 Claims |

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1. A semiconductor device comprising:
fins representing active regions, the fins extending in a first direction;
gate structures correspondingly over the fins and extending in a second direction perpendicular to the first direction;
the fins being configured to have a first conductivity type (F-fin) or a different second conductivity type (S-fin);
the fins being aligned along tracks and arranged in rows;
a first one of the rows (first row) having a single-row height relative to the second direction, top and bottom boundaries of the first row being aligned with corresponding ones of the tracks;
the first row including an alpha-type (α-type) cell region and a beta-type (β-type) cell region each of which has the single-row height;
the α-type cell region including a first F-fin, a first S-fin and a first gate structure,
top and bottom edges of the α-type cell region being co-track aligned correspondingly with the top and bottom boundaries of the first row and free from being overlapped by the first F-fin or the first S-fin, and
the first gate structure overlapping each of the first F-fin and the first S-fin and being free from overlapping the top and bottom edges of the α-type cell region; and
the β-type cell region including a second F-fin, a second S-fin, a third F-fin, a third S-fin and a second gate structure;
the second gate structure overlapping each of the second F-fin and the second S-fin, and further overlapping at least one of the third F-fin or the third S-fin;
a top edge of the β-type cell region being co-track aligned with the top boundary of the first row and co-track aligned with the third F-fin; and
a bottom edge of the β-type cell region being co-track aligned with the bottom boundary of the first row and co-track aligned with the third S-fin.
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