US 12,423,504 B1
Adaptive path based analysis process
Umesh Gupta, Noida (IN); Marut Agarwal, Ghaziabad (IN); Satyendra Patel, Noida (IN); Naresh Kumar, Uttar Pradesh (IN); Prashant Sethia, San Jose, CA (US); Ankit Sethi, Delhi (IN); and Shubham Kumar, Mohali (IN)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Aug. 24, 2022, as Appl. No. 17/894,236.
Int. Cl. G06F 30/398 (2020.01); G06F 30/27 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 30/27 (2020.01); G06F 2119/12 (2020.01)] 13 Claims
OG exemplary drawing
 
1. A computer-implemented method comprising:
loading one or more libraries, netlists, or constraints associated with an electronic design;
loading parasitic data associated with the electronic design;
performing a self adaptive, infinite depth, path based analysis on one or more timing analysis views associated with the electronic design; and
analyzing the electronic design based upon, at least in part, the self adaptive, infinite depth, path based analysis, wherein the self adaptive, infinite depth, path based analysis includes an endpoint violation level analysis; and
performing a full depth analysis for an endpoint having a high level violation, wherein performing a full depth analysis for an endpoint having a high level violation includes identifying all endpoint violations associated with the electronic design.