| CPC G06F 30/396 (2020.01) [G06F 30/327 (2020.01); G06F 30/20 (2020.01); G06F 30/3312 (2020.01); G06F 30/3315 (2020.01); G06F 30/337 (2020.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 2117/10 (2020.01)] | 20 Claims |
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1. A method comprising:
accessing, from memory, a circuit design comprising a clock tree that interconnects a clock source to a plurality of clock sinks, each clock sink in the plurality of clock sinks having an associated target insertion delay adjustment, the clock tree being generated based on application of a restriction on a quantity of levels of components in the clock tree for respectively adding delay to the clock source;
identifying an individual target insertion delay adjustment associated with an individual clock sink of the plurality of clock sinks;
comparing the individual target insertion delay adjustment to a threshold value;
selectively removing application of the restriction on the quantity of levels of components to provide the individual target insertion delay adjustment based on comparing the individual target insertion delay adjustment to the threshold value; and
modifying at least a portion of the clock tree based on application of the restriction after the selectively removing.
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