US 12,423,415 B2
Dynamic hardware integrity and/or replay protection
Siddhartha Chhabra, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 18/266,379
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Dec. 26, 2020, PCT No. PCT/US2020/067064
§ 371(c)(1), (2) Date Jun. 9, 2023,
PCT Pub. No. WO2022/139848, PCT Pub. Date Jun. 30, 2022.
Prior Publication US 2024/0193263 A1, Jun. 13, 2024
Int. Cl. G06F 21/54 (2013.01); G06F 11/10 (2006.01); G06F 21/60 (2013.01)
CPC G06F 21/54 (2013.01) [G06F 11/1016 (2013.01); G06F 21/602 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one memory security engine;
decoder circuitry to decode a single instruction, the single instruction to including:
a field for an opcode, the opcode to indicate that execution circuitry is to at least indicate to the at least one memory security engine to configure an integrity based metadata organization region of memory, wherein in the integrity based metadata organization region of memory a dataline is to be stored with a set of metadata that includes a message authentication code and a first proper subset of an error correction code and a second, different proper subset of the error correction code associated with the dataline is to be stored in memory that is sequestered from the dataline and the set of metadata, and
at least one field that is at least one of:
an identifier of at least one operand location that is to store an indication of the region of memory that is to be organized according to the integrity based metadata organization and
an immediate that is to encode an indication of a region of memory that is to be organized according to the integrity based metadata organization; and
the execution circuitry to execute the decoded single instruction according to the opcode.