US 12,423,263 B2
Dual system server
Li-Hong Huang, Shanghai (CN); Muxin Wang, Shanghai (CN); Hong-Chou Lin, Taipei (TW); and Yu-Fan Chen, Taipei (TW)
Assigned to SQ TECHNOLOGY(SHANGHAI) CORPORATION, Shanghai (CN); and INVENTEC CORPORATION, Taipei (TW)
Filed by SQ TECHNOLOGY(SHANGHAI) CORPORATION, Shanghai (CN); and INVENTEC CORPORATION, Taipei (TW)
Filed on Dec. 11, 2023, as Appl. No. 18/535,922.
Claims priority of application No. 202311501867.0 (CN), filed on Nov. 10, 2023.
Prior Publication US 2025/0156368 A1, May 15, 2025
Int. Cl. G06F 15/78 (2006.01); G06F 13/42 (2006.01)
CPC G06F 15/78 (2013.01) [G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A dual system server, comprising:
a central processing unit;
a first baseboard management controller connected to the central processing unit through a first peripheral component interconnect express interface;
a second baseboard management controller connected to the central processing unit through a second peripheral component interconnect express interface;
a complex programmable logic device connected to the first baseboard management controller through a first inter-integrated circuit interface and connected to the second baseboard management controller through a second inter-integrated circuit interface; and
a demultiplex chip connected to the first baseboard management controller, the second baseboard management controller and the complex programmable logic device, wherein the demultiplex chip is configured to enable communication of one of the first inter-integrated circuit interface and the second inter-integrated circuit interface, and disable communication of the other one of the first inter-integrated circuit interface and the second inter-integrated circuit interface.