US 12,423,255 B1
Programmable traffic ingress direction for reduced latency in a DPU
Weihuang Wang, Santa Clara, CA (US); Alessandro Fulli, Boxborough, MA (US); Alexandru Seibulescu, Santa Clara, CA (US); Kecheng Qian, Santa Clara, CA (US); Kit Chiu Chu, Freemont, CA (US); Mahesh Machineni, Santa Clara, CA (US); and Michael Brian Galles, Los Altos, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Mar. 18, 2024, as Appl. No. 18/608,605.
Int. Cl. G06F 13/28 (2006.01)
CPC G06F 13/28 (2013.01) 20 Claims
OG exemplary drawing
 
1. A data processing unit (DPU), comprising:
a networking pipeline;
a direct memory access (DMA) pipeline;
a parser circuit configured to parse a received packet to identify a packet header vector (PHV); and
match circuitry configured to, based on receiving the PHV:
determine that the received packet should bypass the networking pipeline; and
edit the PHV to indicate the received packet should be transmitted to the DMA pipeline.