US 12,423,254 B2
Interrupt latency resilient UART driver
Francois Killeen, Laval (CA); Alexandre Autotte Portelance, St-Hubert (CA); Yacin Belmihoub-Martel, Montréal (CA); Issam Maghni, Saint-Léonard (CA); Jean Francois Deschenes, Ste-Marthe-sur-le-lac (CA); and Simon Beaudoin, Beloeil (CA)
Assigned to Silicon Laboratories Inc., Austin, TX (US)
Filed by Silicon Laboratories Inc., Austin, TX (US)
Filed on Aug. 17, 2023, as Appl. No. 18/235,071.
Prior Publication US 2025/0061073 A1, Feb. 20, 2025
Int. Cl. G06F 13/28 (2006.01); G06F 13/16 (2006.01)
CPC G06F 13/28 (2013.01) [G06F 13/1673 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A peripheral device to receive data from a host with no flow control, wherein the data comprises a plurality of headers and payloads, the peripheral device comprising:
a processing unit;
a memory device; and
a direct memory access (DMA) controller,
wherein the peripheral device configures the DMA controller to receive a header or a payload, uses an active buffer disposed in the memory device to store the header or payload sent to the peripheral device, and uses a spill buffer to capture additional headers and payloads transmitted before the DMA controller is properly configured to receive the additional headers and payloads, and wherein the peripheral device uses an interrupt service routine to process the header or the payload received in the active buffer, and executes a recovery routine, different from the interrupt service routine, when data is written to the spill buffer by the DMA controller, to extract the additional headers and/or payloads in the spill buffer and pass them to higher level software.