| CPC G06F 12/1408 (2013.01) [G06F 3/0622 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
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1. A nonvolatile memory device comprising:
a memory cell array configured to store original setting data;
a page buffer circuit connected to the memory cell array through a plurality of bit-lines;
a secure buffer including an access control circuit and a plurality of registers with restricted access, the plurality of registers configured to store the original setting data that is dumped-down from the memory cell array through the page buffer circuit in an initialization sequence; and
a control circuit configured to control the page buffer circuit and the secure buffer,
wherein the plurality of registers includes a first register and second registers, and
wherein the access control circuit is configured to access, in response to the first register being accessed, at least a portion of the second registers concurrently with accessing the first register.
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