US 12,423,241 B1
Shadow tag management for accelerator partitions
Amit P. Apte, Austin, TX (US); Bryan P. Broussard, Austin, TX (US); Vydhyanathan Kalyanasundharam, Santa Clara, CA (US); and Ganesh Balakrishnan, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 28, 2022, as Appl. No. 18/090,251.
Int. Cl. G06F 12/08 (2016.01); G06F 12/0846 (2016.01)
CPC G06F 12/0851 (2013.01) [G06F 2212/1016 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
interleaving one or more of a plurality of chiplets, each chiplet having a cache, and interleaving the corresponding caches into a larger cache;
identifying an address of the larger cache to be used with a memory request from one of the plurality of chiplets with a source chiplet ID; and
storing, using an indexing scheme that repurposes at least one static address bit to incorporate the source chiplet ID, a shadow tag for one of the caches of the larger cache corresponding to the memory request, wherein the shadow tag indicates a memory address associated with the memory request and a state for corresponding data in the one of the caches.