US 12,423,240 B2
Cache layout optimization
Malak Alshawabkeh, Franklin, MA (US); Kaustubh Sahasrabudhe, Westborough, MA (US); and Ramesh Doddaiah, Westborough, MA (US)
Assigned to Dell Products L.P., Round Rock, TX (US)
Filed by Dell Products L.P., Round Rock, TX (US)
Filed on Nov. 3, 2023, as Appl. No. 18/386,683.
Prior Publication US 2025/0147891 A1, May 8, 2025
Int. Cl. G06F 12/0846 (2016.01); G06F 12/0802 (2016.01)
CPC G06F 12/0848 (2013.01) [G06F 12/0802 (2013.01); G06F 2212/282 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving an input/output (IO) workload by a storage array; and
dynamically adjusting cache slot allocations for each cache segment of global memory based on one or more characteristics of the IO workload, wherein dynamically adjusting cache slot allocations comprises:
analyzing the IO workload using a neural self-learning architecture to process current and historical IO metadata,
generating cache layout models using a holt-winters forecasting technique,
establishing distinct cache slot sizes for different cache segments,
determining IO characteristics, including IO type, size, pattern, and sequence, and
generating time-series signals corresponding to the IO workload based on cache types and cache segments targeted by IO messages of the IO workload, wherein the time-series signals are processed using the holt-winters forecasting technique to generate the cache layout models defining sizes of mirrored and unmirrored cache partitions and quantities of cache slots allocated to cache segments within each partition.