US 12,423,237 B2
Data processing network with super home node
Wenxuan Zhang, Austin, TX (US); Jamshed Jalal, Austin, TX (US); Mark David Werkheiser, Austin, TX (US); Sakshi Verma, Austin, TX (US); Ritukar Khanna, Austin, TX (US); Devi Sravanthi Yalamarthy, Austin, TX (US); Gurunath Ramagiri, Austin, TX (US); Mukesh Patel, Round Rock, TX (US); and Tushar P Ringe, Austin, TX (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Feb. 14, 2023, as Appl. No. 18/109,453.
Prior Publication US 2024/0273025 A1, Aug. 15, 2024
Int. Cl. G06F 12/0831 (2016.01); G06F 12/0871 (2016.01)
CPC G06F 12/0833 (2013.01) [G06F 12/0871 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A data processing apparatus comprising:
a coherence manager, of a first integrated circuit, configured to manage cache lines mapped to addresses in a first memory coupled to or located in the first integrated circuit, or mapped to addresses in one or more second memories, each second memory coupled to or located in a second integrated circuit of one or more second integrated circuits;
where the coherence manager is further configured to store a plurality of entries in a snoop filter table, each entry in the snoop filter table associated with a cache line and including a presence vector including:
one or more first bits, each first bit designated as corresponding to a specific caching agent of a plurality of caching agents of the first integrated circuit, each first bit indicating when the cache line is present at the specific caching agent; and
one or more second bits, each second bit designated as corresponding to a specific second integrated circuit of the one or more second integrated circuits, each second bit indicating when the cache line is mapped to an address in the first memory and is present at any caching agent of a plurality of caching agents of the specific second integrated circuit.