US 12,423,233 B2
Order enforcement for delegable memory accesses
Yohan Fernand Fargeix, Nice (FR); Geoffray Matthieu Lacourba, Nice (FR); Albin Pierrick Tonnerre, Nice (FR); Paolo Monti, Quattordio (IT); and Abhishek Raja, Niagara Falls, NY (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Nov. 29, 2023, as Appl. No. 18/523,249.
Prior Publication US 2025/0173265 A1, May 29, 2025
Int. Cl. G06F 12/0804 (2016.01); G06F 12/0873 (2016.01)
CPC G06F 12/0804 (2013.01) [G06F 12/0873 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
memory access circuitry configured to perform memory accesses in response to memory access instructions among a series of instructions to be executed;
offloading circuitry configured to:
identify, in the series of instructions, a delegable memory access instruction specifying a delegable memory access to be performed to a target address by an external processing apparatus instead of the delegable memory access being performed by the memory access circuitry; and
dependent on the delegable memory access instruction being committed, to send a request to the external processing apparatus to request that the external processing apparatus performs the delegable memory access specified by the delegable memory access instruction;
tracking circuitry configured to maintain tracking information representing the target address of the delegable memory access in a delegable memory access tracking structure separate from a tracking structure used to track non-delegable memory accesses to be performed by the memory access circuitry; and
order enforcement circuitry configured to enforce an ordering requirement between a given non-delegable memory access and the delegable memory access based on a lookup of address information associated with the given non-delegable memory access in the delegable memory access tracking structure.