US 12,423,232 B2
Memory device with on-die cache
Sean S. Eilert, Penryn, CA (US); Ameen D. Akel, Rancho Cordova, CA (US); and Shivam Swami, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 28, 2024, as Appl. No. 18/590,173.
Application 18/590,173 is a continuation of application No. 17/100,453, filed on Nov. 20, 2020, granted, now 11,947,453.
Claims priority of provisional application 63/093,412, filed on Oct. 19, 2020.
Prior Publication US 2024/0202119 A1, Jun. 20, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0802 (2016.01); G06F 3/06 (2006.01)
CPC G06F 12/0802 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 2212/22 (2013.01); G06F 2212/221 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of memory banks;
a plurality of row buffers, wherein at least one row buffer of the plurality of row buffers is associated with each memory bank of the plurality of memory banks;
a cache comprising a plurality of cache lines;
a processing logic communicatively coupled to the plurality of memory banks and the plurality of row buffers, the processing logic to perform operations comprising:
receiving an activate command comprising a cache hint and an identifier of a row of a memory bank of the plurality of memory banks, wherein the cache hint comprises a dedicated bit in the activate command that indicates whether to cache or exclude from caching data of the identified row;
fetching the data from the row identified by the activate command to a row buffer of the plurality of row buffers; and
copying, based on the cache hint, the data to a cache line of the plurality of cache lines.