| CPC G06F 9/505 (2013.01) [G01N 30/8644 (2013.01); G06F 1/329 (2013.01); G06F 9/5038 (2013.01); G06F 9/5061 (2013.01); G06F 9/5066 (2013.01); G06N 3/02 (2013.01); G06N 3/04 (2013.01); G06N 5/01 (2023.01); G06F 2209/5017 (2013.01)] | 15 Claims |

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1. A processor, comprising
a task segmentation circuit configured to segment a task into multiple subtasks according to a task segmentation granularity; and
a hardware resource division circuit configured to divide hardware resources of the processor respectively for the multiple subtasks,
wherein the task segmentation circuit includes a task segmentation granularity selection circuit configured to determine the task segmentation granularity, and
a granularity task segmentation circuit that includes:
a first granularity task segmentation circuit configured to take the whole task;
a second granularity task segmentation circuit configured to:
divide sample data associated with the task into one or more subset of sample data, and
identify a computation of each subset of sample data as one of the subtasks;
a third granularity task segmentation circuit configured to segment the task according to layer types of a neural network, where computation for layers of the same layer type is identified as one of the subtasks;
a fourth granularity task segmentation circuit configured to segment the task according to an interlayer structure of the neural network, wherein computation for multiple adjacent layers is identified as one of the subtasks; and
a fifth granularity task segmentation circuit configured to segment the task according to intra-layer structures of the neural network to segment computation types in each of the layers of the neural network into subtasks.
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