US 12,423,145 B2
Hardware accelerators using shared interface registers
Mahesh B. Chappalli, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jan. 23, 2024, as Appl. No. 18/420,602.
Application 18/420,602 is a continuation of application No. 17/149,422, filed on Jan. 14, 2021, granted, now 11,893,419.
Claims priority of provisional application 63/072,089, filed on Aug. 28, 2020.
Prior Publication US 2024/0160479 A1, May 16, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01)
CPC G06F 9/5016 (2013.01) [G06F 9/4812 (2013.01); G06F 9/485 (2013.01); G06F 9/4881 (2013.01)] 20 Claims
OG exemplary drawing
 
1. Non-transitory, computer-readable medium storing instructions that, when executed by a processor, cause the processor to:
initiate a first process in a first hardware accelerator configured to aid the processor by performing the first process, wherein initiating the first process comprises using one or more interface registers;
perform additional processing while the first hardware accelerator performs the first process;
during the first process, initiate a second process in a second hardware accelerator configured to aid the processor in performing the second process, wherein the second hardware accelerator comprises a blocking accelerator that aids in the second process without using the one or more interface registers, and the second hardware accelerator has no access to the one or more interface registers; and
receive an indication via the one or more interface registers to indicate that the first hardware accelerator has completed the first process and that the processor is to operate on results from the first process.