US 12,423,102 B2
Instructions to convert from FP16 to BF8
Alexander Heinecke, San Jose, CA (US); Naveen Mellempudi, Bangalore (IN); Robert Valentine, Kiryat Tivon (IL); Mark Charney, Lexington, MA (US); Christopher Hughes, Santa Clara, CA (US); Evangelos Georganas, San Mateo, CA (US); Zeev Sperber, Zichron Yackov (IL); Amit Gradstein, Binyamina (IL); and Simon Rubanovich, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 26, 2020, as Appl. No. 17/134,353.
Prior Publication US 2022/0206805 A1, Jun. 30, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 7/49 (2006.01); G06F 7/499 (2006.01); H03M 7/24 (2006.01)
CPC G06F 9/30145 (2013.01) [G06F 7/49947 (2013.01); G06F 9/30025 (2013.01); G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); H03M 7/24 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of memory controllers;
a level-two (L2) cache memory coupled to the plurality of memory controllers;
a processor coupled to the plurality of memory controllers, and coupled to the L2 cache memory, the processor having a plurality of cores and a plurality of levels of cache memory, the cores including circuitry to perform operations corresponding to an instruction, the instruction to identify a source register that is to include a plurality of half-precision floating-point data elements and to identify a destination register, wherein the half-precision floating-point data elements are 16-bit data elements, the operations including to:
convert the plurality of half-precision floating-point data elements to a plurality of corresponding 8-bit floating-point data elements, wherein, when one or more of the half-precision floating-point data elements are normal numbers, conversion of the one or more normal numbers to one or more corresponding 8-bit floating-point data elements is to be performed according to a round to nearest even rounding mode, and the one or more corresponding 8-bit floating-point data elements are each to include one sign bit, five exponent bits, and two mantissa bits, wherein for each normal half-precision floating-point data element, a corresponding 8-bit floating-point data element is to be converted from the half-precision floating point data element using a rounding bias; and
store the plurality of 8-bit floating-point data elements in the destination register;
an interconnect interface coupled to the processor; and
a bus controller interface coupled to the processor.