US 12,423,096 B2
Methods and devices for signal processing
Deepak Dasalukunte, Beaverton, OR (US); Richard Dorrance, Hillsboro, OR (US); and Lu Lu, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2021, as Appl. No. 17/560,298.
Prior Publication US 2023/0205519 A1, Jun. 29, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/3001 (2013.01) [G06F 9/3887 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A processor comprising:
an interface configured to receive input data and instructions, and to provide processed data, wherein the received input data comprises data representing a plurality of subband signals of a received radio communication signal;
a shared memory configured to store the received input data;
an instruction memory configured to store the received instructions;
a plurality of processing elements configured to perform a first set of arithmetic operations, wherein each processing element of the plurality of processing elements is configured to perform the first set of arithmetic operations on a subband data representing a subband signal of the received radio communication signal;
a controller configured to control the plurality of processing elements and one or more accelerators based on the received instructions, by which the plurality of processing elements performs the first set of arithmetic operations and the one or more accelerators perform a second set of arithmetic operations based on the received input data stored in the shared memory to obtain the processed data.