US 12,423,076 B1
Code generation based on processor usage
Jaydeep Marathe, Kirkland, WA (US); Michael Murphy, Newark, CA (US); and Xiaohua Zhang, San Jose, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Oct. 12, 2021, as Appl. No. 17/499,438.
Int. Cl. G06F 8/41 (2018.01); G06F 8/30 (2018.01); G06F 8/54 (2018.01)
CPC G06F 8/447 (2013.01) [G06F 8/30 (2013.01); G06F 8/54 (2013.01)] 39 Claims
OG exemplary drawing
 
1. One or more processors comprising:
processing circuitry to:
generate first device code by removing one or more code elements from second device code based on reference information, in host code, indicating one or more code elements that are not to be performed.