US 12,423,075 B2
Code prefetch instruction
Ahmad Yasin, Haifa (IL); Lihu Rappoport, Haifa (IL); Jared W. Stark, Portland, OR (US); Jeffrey Baxter, Cupertino, CA (US); Israel Diamand, Aderet (IL); Pavel Fridman, Haifa (IL); Ibrahim Hur, Portland, OR (US); and Nir Tell, Atlit (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 26, 2020, as Appl. No. 17/033,751.
Claims priority of provisional application 63/017,585, filed on Apr. 29, 2020.
Prior Publication US 2021/0342134 A1, Nov. 4, 2021
Int. Cl. G06F 9/44 (2018.01); G06F 8/41 (2018.01)
CPC G06F 8/4442 (2013.01) 17 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an instruction decoder to decode a code prefetch instruction, wherein the code prefetch instruction is to specify a relative address of a first instruction to be prefetched;
load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction; and
execution circuitry to execute the first instruction at a fetch stage of a pipeline instead of at an execute stage of the pipeline.