US 12,423,059 B2
Input sequence re-ordering method and input sequence re-ordering unit with multi input-precision reconfigurable scheme and pipeline scheme for computing-in-memory macro in convolutional neural network application
Yen-Cheng Chiu, Hsinchu (TW); Ta-Wei Liu, Hsinchu (TW); Fu-Chun Chang, Hsinchu (TW); and Meng-Fan Chang, Hsinchu (TW)
Assigned to NATIONAL TSING HUA UNIVERSITY, Hsinchu (TW)
Filed by NATIONAL TSING HUA UNIVERSITY, Hsinchu (TW)
Filed on Jun. 8, 2021, as Appl. No. 17/341,408.
Prior Publication US 2022/0391691 A1, Dec. 8, 2022
Int. Cl. G06F 7/76 (2006.01); G06F 7/08 (2006.01); G06F 7/544 (2006.01)
CPC G06F 7/76 (2013.01) [G06F 7/08 (2013.01); G06F 7/5443 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An input sequence re-ordering method with a multi input-precision reconfigurable scheme and a pipeline scheme for a computing-in-memory macro in a convolutional neural network application, which is configured to re-order a plurality of multi-bit input signals, and the input sequence re-ordering method with the multi input-precision reconfigurable scheme and the pipeline scheme for the computing-in-memory macro in the convolutional neural network application comprising:
performing a scanning step, wherein the scanning step comprises driving a scanner to scan one group of the plurality of multi-bit input signals to determine whether an initial value of one of a plurality of flag signals in one of a plurality of multi-bit section flags is changed to an inverted initial value according to a plurality of bit numbers of the one group of the plurality of multi-bit input signals, and the initial value is different from the inverted initial value; and
performing a re-ordering step, wherein the re-ordering step comprises driving a sorter to select a part of the one group of the plurality of multi-bit input signals corresponding to a plurality of inverted initial values of the plurality of flag signals in the one of the plurality of multi-bit section flags, and then transmit the part of the one group of the plurality of multi-bit input signals to the computing-in-memory macro;
wherein the plurality of multi-bit section flags comprise:
a first multi-bit section flag configured to label at least one N-bit input signal of the plurality of multi-bit input signals, wherein the first multi-bit section flag comprises a plurality of first flag signals, a number of the plurality of first flag signals is equal to a number of the plurality of multi-bit input signals, the plurality of first flag signals are corresponding to the plurality of multi-bit input signals, respectively, the at least one N-bit input signal is represented by an N bit value, and N is a positive integer; and
a second multi-bit section flag configured to label at least one M-bit input signal of the plurality of multi-bit input signals, wherein the second multi-bit section flag comprises a plurality of second flag signals, a number of the plurality of second flag signals is equal to the number of the plurality of multi-bit input signals, the plurality of second flag signals are corresponding to the plurality of multi-bit input signals, respectively,
the at least one M-bit input signal is represented by an M bit value, and
M is a positive integer greater than N;
wherein the scanning step further comprises:
performing a first scanning sub-step, wherein the first scanning sub-step comprises driving the scanner to scan the one group of the plurality of multi-bit input signals to obtain the plurality of bit numbers of the one group of the plurality of multi-bit input signals; and
performing a second scanning sub-step, wherein the second scanning sub-step comprises driving the sorter to determine whether the initial value of one of the plurality of first flag signals of the first multi-bit section flag and the plurality of second flag signals of the second multi-bit section flag is changed to the inverted initial value according to one of the plurality of bit numbers of the one group of the plurality of multi-bit input signals;
wherein in the second scanning sub-step, in response to determining that the one of the plurality of bit numbers of the one group of the plurality of multi-bit input signals is equal to N, the initial value of one of the plurality of first flag signals of the first multi-bit section flag is changed to the inverted initial value, the initial value of one of the plurality of second flag signals of the second multi-bit section flag is not changed, and a first count number of a first counter of the sorter is added by 1;
wherein the first count number represents a number of a plurality of the plurality of first flag signals which are all equal to the inverted initial value in the first multi-bit section flag.