US 12,423,056 B2
Multiply-accumulate unit
Seung-Hwan Song, Palo Alto, CA (US); Sang-Soo Lee, Cupertino, CA (US); and Sihwan Kim, San Francisco, CA (US)
Assigned to Anaflash Inc., San Jose, CA (US)
Filed by ANAFLASH INC., San Jose, CA (US)
Filed on Sep. 16, 2020, as Appl. No. 17/022,137.
Claims priority of provisional application 62/901,270, filed on Sep. 17, 2019.
Prior Publication US 2021/0081175 A1, Mar. 18, 2021
Int. Cl. G06F 7/544 (2006.01); G06G 7/16 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01)
CPC G06F 7/5443 (2013.01) [G06G 7/16 (2013.01); G11C 16/0433 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An analog multiplier accumulator array, comprising:
analog multipliers organized in a matrix of rows and columns,
one or more than one analog input signal line coupled to an analog multiplier in a row of the array;
an analog level sensing circuit;
a set of one or more than one bit line, each bit line electrically connected to an analog multiplier in each column of the row; and
an analog accumulator configured to connect the set of bit line to the analog level sensing circuit configured to generate digital output signals,
wherein each analog multiplier comprises an access transistor connected to the analog input signal line and a variable resistor; and
wherein the analog accumulator comprises:
an array of metal-oxide semiconductor (MOS) transistors in a row, each MOS transistor connected to a bit line in the set of bit lines; and
one control line, connected to respective gates of the MOS transistors, configured to activate the MOS transistors such that current flowing in the bit lines connected to the MOS transistors are allowed to be merged in one of the connected bit lines when the MOS transistors are activated.