| CPC G06F 7/505 (2013.01) [G06F 7/504 (2013.01)] | 11 Claims |
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1. A processor-implemented method of a processor including a plurality of adder circuitries, the method comprising:
generating a plurality of sub-operands, respectively corresponding to bit values of bit sections of a plurality of operands of an input feature map of a neural network, having a first pixel configuration, by dividing the plurality of operands into the bit sections each having a predetermined bit size, wherein each of the plurality of operands has an n-bit precision, and n is a natural number;
generating respective intermediate bit results by operating the plurality of adder circuitries in parallel through each of the plurality of adder circuitries being provided respective multiple sub-operands of the plurality of sub-operands;
generating an output feature map, having a second pixel configuration different from the first pixel configuration, by combining bit-shifted intermediate bit results that result from respective bit-shiftings of the respective intermediate bit results based on respective bit positions in the plurality of operands, such that the combined bit-shifted intermediate bit results correspond to a summation result for the plurality of operands; and
dependent on a performed determination that there is a zero-bit section, among the bit sections, in which a corresponding sub-operand has a zero-value:
in the operating of the plurality of adder circuitries in parallel, controlling a corresponding one adder circuitry, of the plurality of adder circuitries, allocated to the zero-bit section to not operate with respect to the corresponding sub-operand, thereby skipping performance of an add operation with respect to the corresponding sub-operand; and
controlling the corresponding one adder circuitry to operate with respect to an other operand, other than the plurality of operands, to decrease an idling of the corresponding one adder circuitry.
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