US 12,423,019 B2
Read gate training and tracking
David Da Wei Lin, Westborough, MA (US); Ronald Lee Pettyjohn, Concord, MA (US); Pouya Najafi Ashtiani, Toronto (CA); Gershom Birk, Coquitlam (CA); and Anwar Parvez Kashem, Sudbury, MA (US)
Assigned to Advanced Micro Devices, Inc, Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed by Advanced Micro Devices, Inc, Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed on Jun. 27, 2023, as Appl. No. 18/342,186.
Prior Publication US 2025/0004662 A1, Jan. 2, 2025
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computing device, comprising:
a PHY configured to:
communicate, to a memory system, a memory read operation that includes a memory clock which correlates to a physical layer (PHY) clock;
receive a return data signal from the memory system, the return data signal including a returned data strobe that is out-of-phase with respect to the PHY clock; and
filter, using edge detection and delay adjustment, a high impedance state of the returned data strobe with respect to the PHY clock.