US 12,423,010 B2
Memory devices with multiple sets of latencies and methods for operating the same
Dean D. Gans, Nampa, ID (US); Yoshiro Riho, Tokyo (JP); Shunichi Saito, Kanagawa (JP); and Osamu Nagashima, Tokyo (JP)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Feb. 16, 2024, as Appl. No. 18/444,215.
Application 18/444,215 is a continuation of application No. 17/392,085, filed on Aug. 2, 2021, granted, now 11,914,874.
Application 17/392,085 is a continuation of application No. 16/543,467, filed on Aug. 16, 2019, granted, now 11,150,821, issued on Oct. 19, 2021.
Application 16/543,467 is a continuation of application No. 16/048,078, filed on Jul. 27, 2018, granted, now 10,976,945, issued on Apr. 13, 2021.
Application 16/048,078 is a continuation of application No. 15/798,083, filed on Oct. 30, 2017, granted, now 10,481,819, issued on Nov. 19, 2019.
Prior Publication US 2024/0184467 A1, Jun. 6, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01)
CPC G06F 3/0634 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0611 (2013.01); G06F 3/0673 (2013.01); G06F 13/16 (2013.01); G11C 7/1045 (2013.01); G11C 2207/2272 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a dynamic random access memory (DRAM) device, comprising:
determining a quantity of operating features that are enabled from a plurality of operating features supported by the DRAM device, the quantity of enabled operating features comprising a byte mode feature associated with operation of the DRAM device, a read data copy feature associated with operation of the DRAM device, or both;
selecting a set of latency values from a plurality of sets of latency values based at least in part on the quantity of operating features that are enabled, wherein the plurality of sets of latency values is selected based at least in part on whether dynamic voltage and frequency scaling (DVFS) is disabled or enabled at the DRAM device;
selecting a latency value from the set of latency values based at least in part on a value of a mode register; and
executing a read command based at least in part on the selected latency value.