US 12,423,009 B2
Concurrent write data strobe and reference voltage calibrations
Robert E. Jeter, Santa Clara, CA (US); Jingkui Zheng, Sunnyvale, CA (US); David A. Knopf, San Jose, CA (US); Satish B. Dulam, Sunnyvale, CA (US); Kai Lun Hsiung, Fremont, CA (US); Venkata Ramana Malladi, Santa Clara, CA (US); and Rahul Ranjan, Campbell, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Mar. 5, 2024, as Appl. No. 18/596,046.
Application 18/596,046 is a continuation of application No. 17/929,191, filed on Sep. 1, 2022, granted, now 11,960,739.
Prior Publication US 2024/0211151 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G11C 7/22 (2006.01)
CPC G06F 3/0632 (2013.01) [G06F 3/0614 (2013.01); G06F 3/0658 (2013.01); G06F 3/0673 (2013.01); G11C 7/22 (2013.01); G11C 2207/2254 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory controller circuit configured to convey a write clock signal to a memory, wherein the memory controller circuit includes:
a calibration circuit configured to send a first command to memory to initiate a calibration of the write clock signal and, after an amount of time has elapsed, receive a calibration value from the memory; and
a delay circuit configured to apply a delay to the write clock signal, wherein the calibration circuit is configured to complete calibration of the write clock signal by adjusting the delay applied to the write clock signal in accordance with the calibration value;
wherein the calibration circuit is further configured to perform a reference voltage calibration concurrent with the calibration of the write clock signal.