US 12,423,006 B2
Low power memory state during non-idle processor state
Benjamin Tsien, Santa Clara, CA (US); Chintan S. Patel, Austin, TX (US); and Guhan Krishnan, Boxborough, MA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 30, 2023, as Appl. No. 18/345,927.
Prior Publication US 2025/0004652 A1, Jan. 2, 2025
Int. Cl. G06F 3/06 (2006.01); G06F 12/0802 (2016.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0634 (2013.01); G06F 3/0673 (2013.01); G06F 12/0802 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first processing component;
a second processing component;
a cache; and
a control circuit configured to:
instruct the first processing component to avoid allocating in the cache in response to cache misses;
instruct the second processing component to allocate in the cache while the first processing component avoids allocating in the cache; and
instruct a memory device to enter a low power state in response to an idle state of the memory device.