US 12,423,001 B2
Memory device and operating method thereof
Seong-Jin Cho, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 14, 2022, as Appl. No. 17/986,418.
Claims priority of application No. 10-2022-0004055 (KR), filed on Jan. 11, 2022; and application No. 10-2022-0047061 (KR), filed on Apr. 15, 2022.
Prior Publication US 2023/0221871 A1, Jul. 13, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array comprising a plurality of memory cell rows;
a monitoring cell array configured to detect a victim memory cell row of the plurality of memory cell rows, and to generate bit data in response to the victim memory cell row being affected by a row hammering operation;
a bit data decoder configured to:
receive the bit data, and
based on the bit data, generate a victim memory address comprising address information about the victim memory cell row; and
a refresh manager configured to perform a refresh operation on the victim memory cell row based on the victim memory address.