US 12,422,987 B2
Portioned erase operation for a memory system
Sridhar Prudviraj Gunda, Bangalore (IN); Amiya Banerjee, Bangalore (IN); Ritesh Tiwari, Bangalore (IN); and Shreesha Prabhu, Singapore (SG)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 8, 2023, as Appl. No. 18/504,992.
Claims priority of provisional application 63/385,474, filed on Nov. 30, 2022.
Prior Publication US 2024/0176491 A1, May 30, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 12/0246 (2013.01); G06F 2212/7205 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices comprising a block of memory cells; and
processing circuitry associated with the memory system, wherein the processing circuitry is configured to cause the memory system to:
perform, on the block of memory cells, a first portion of an erase operation;
receive a write command to write data to the block of memory cells after performing the first portion of the erase operation;
determine whether a threshold voltage of the block of memory cells satisfies a threshold based at least in part on receiving the write command, the threshold voltage corresponding to a read window for the block of memory cells; and
perform, on the block of memory cells, a second portion of the erase operation based at least in part on determining that the threshold voltage satisfies the threshold and based at least in part on receiving the write command.