US 12,422,914 B2
Dynamic power management among multiple memory devices
Niels Reimers, Meadow Vista, CA (US); and Andrew Morning-Smith, Vancouver (CA)
Assigned to SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed by SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed on Sep. 29, 2023, as Appl. No. 18/375,362.
Prior Publication US 2025/0110542 A1, Apr. 3, 2025
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/26 (2006.01); G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 1/3296 (2019.01)
CPC G06F 1/3275 (2013.01) [G06F 1/3296 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for dynamic power management, comprising:
at a plurality of memory devices coupled into a ring of memory devices:
passing a power data packet along a power control path that tracks the ring of memory devices continuously, including at a first memory device and during a current cycle:
receiving the power data packet from an upstream memory device on the power control path, wherein the power data packet includes at least a system power level indicating total power consumption of the plurality of memory devices;
setting a current power level of the first memory device based on the received power data packet;
updating the power data packet based on the current power level; and
sending the updated power data packet to a downstream memory device on the power control path.