US 12,422,913 B1
Power management for a graphics processing unit or other circuit
Patrick Y. Law, Cupertino, CA (US); Robert A. Drebin, Palo Alto, CA (US); Keith Cox, Sunnyvale, CA (US); and James S. Ismail, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Nov. 1, 2022, as Appl. No. 18/051,820.
Application 18/051,820 is a continuation of application No. 17/221,076, filed on Apr. 2, 2021, granted, now 11,513,585.
Application 17/221,076 is a continuation of application No. 16/139,631, filed on Sep. 24, 2018, granted, now 11,009,938, issued on Apr. 28, 2021.
Application 16/139,631 is a continuation of application No. 15/284,660, filed on Oct. 4, 2016, granted, now 10,114,446, issued on Oct. 30, 2018.
Application 15/284,660 is a continuation of application No. 14/549,656, filed on Nov. 21, 2014, granted, now 9,494,994, issued on Nov. 15, 2016.
Application 14/549,656 is a continuation of application No. 13/090,459, filed on Apr. 20, 2011, granted, now 8,924,752, issued on Dec. 30, 2014.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/32 (2019.01); G06F 1/20 (2006.01); G06F 1/3203 (2019.01); G06F 1/3206 (2019.01); G06F 1/3218 (2019.01); G06F 1/3234 (2019.01); G06F 1/324 (2019.01); G06F 1/3287 (2019.01); G06F 1/3296 (2019.01)
CPC G06F 1/3265 (2013.01) [G06F 1/206 (2013.01); G06F 1/3203 (2013.01); G06F 1/3206 (2013.01); G06F 1/3218 (2013.01); G06F 1/324 (2013.01); G06F 1/3287 (2013.01); G06F 1/3296 (2013.01); Y02D 10/00 (2018.01)] 17 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a processor;
power monitor circuitry coupled to the processor and configured to generate a power measurement representing power consumed in the processor; and
controller circuitry coupled to the power monitor circuitry and the processor and configured to implement a feedback loop to perform the following procedure multiple times:
generate a target power measurement based on an amount of remaining battery life in a battery that is a source of power to the integrated circuit;
determine an error between the target power measurement and a power measurement generated by the power monitor circuitry;
based on the determined error:
select a limit for a first amount of time within a given fixed time period that the processor is powered on to no more than a first limit amount such that the processor is powered off during a remainder of the fixed time period beyond the limit, wherein the controller circuitry is configured to determine the limit amount at a current powered first operating point of the processor having a first non-zero frequency and a first non-zero supply voltage; and
alter a subsequent powered operating point of the processor to a powered second operating point, having a second non-zero frequency and a second non-zero supply voltage, including to select the second operating point based on a non-zero length of the first amount of time.