US 12,422,912 B2
Electronic system and protection method for power management circuit
Kuan-Wen Su, Hsinchu (TW); Shu-Ching Lin, Hsinchu (TW); Chien-Yu Lan, Hsinchu (TW); and Shang-Wei Chen, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsinchu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/446,619.
Prior Publication US 2025/0053220 A1, Feb. 13, 2025
Int. Cl. G06F 1/3206 (2019.01); G06F 1/26 (2006.01); G06F 1/28 (2006.01); G06F 9/30 (2018.01); G06F 11/00 (2006.01); G06F 21/81 (2013.01)
CPC G06F 1/3206 (2013.01) [G06F 1/26 (2013.01); G06F 1/28 (2013.01); G06F 9/30101 (2013.01); G06F 11/00 (2013.01); G06F 21/81 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic system comprising:
a processor generating and outputting a first data frame, wherein the first data frame comprises at least one first guard bit and a first address; and
a first power management circuit comprising a first register, receiving the first data frame, and determining legitimacy of the first address according to the least one first guard bit,
wherein in response to that the first address is legal, the power management circuit transmits a first response to the processor and accesses a first region in the first register according to the first address.