US 12,422,907 B2
Semiconductor package and thermal management method thereof
Jungpil Lee, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 2, 2022, as Appl. No. 17/879,089.
Claims priority of application No. 10-2021-0138940 (KR), filed on Oct. 19, 2021.
Prior Publication US 2023/0121072 A1, Apr. 20, 2023
Int. Cl. G06F 1/20 (2006.01); G06F 1/3206 (2019.01); G06F 1/3237 (2019.01); G06F 1/324 (2019.01); G06F 1/3287 (2019.01); H01L 23/34 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01)
CPC G06F 1/206 (2013.01) [G06F 1/3206 (2013.01); G06F 1/3237 (2013.01); G06F 1/324 (2013.01); G06F 1/3287 (2013.01); H01L 23/34 (2013.01); H01L 23/481 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/1426 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a lower semiconductor chip including a plurality of through electrodes; and
an upper semiconductor chip mounted to an upper surface of the lower semiconductor chip,
wherein the lower semiconductor chip is electrically connected to the upper semiconductor chip via the plurality of through electrodes, and
wherein the lower semiconductor chip includes
at least one temperature sensor configured to sense a temperature of the upper semiconductor chip,
a power control unit connected to the at least one temperature sensor,
a power switching element connected to at least a first one of the plurality of through electrodes, and
a clock control element connected to at least a second one of the plurality of through electrodes, and
wherein the upper semiconductor chip includes a plurality of regions,
the at least one temperature sensor includes a plurality of temperature sensors corresponding to the plurality of regions, and
the plurality of temperature sensors vertically overlap the plurality of regions of the upper semiconductor chip, respectively.