US 12,422,877 B2
Voltage reference circuit and method for providing reference voltage
Yen-Ting Wang, Round Rock, TX (US); Alan Roth, Leander, TX (US); Eric Soenen, Austin, TX (US); Alexander Kalnitsky, San Francisco, CA (US); Liang-Tai Kuo, Zhudong Township, Hsinchu County (TW); and Hsin-Li Cheng, Hsin Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 8, 2024, as Appl. No. 18/765,706.
Application 18/765,706 is a continuation of application No. 18/308,887, filed on Apr. 28, 2023, granted, now 12,072,726.
Application 18/308,887 is a continuation of application No. 17/143,369, filed on Jan. 7, 2021, granted, now 11,675,383, issued on Jun. 13, 2023.
Claims priority of provisional application 62/977,437, filed on Feb. 17, 2020.
Prior Publication US 2024/0361795 A1, Oct. 31, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G05F 3/26 (2006.01); G05F 3/24 (2006.01)
CPC G05F 3/262 (2013.01) [G05F 3/24 (2013.01); G05F 3/247 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A voltage reference circuit, comprising:
a transistor;
a flipped-gate transistor, wherein a gate and a drain of the flipped-gate transistor are coupled to a gate and a drain of the transistor, and a bulk and a source of the flipped-gate transistor are coupled to a ground;
a first current mirror unit configured to provide a first current to the flipped-gate transistor and a mirroring current in response to a bias current;
a second current mirror unit configured to drain a second current from the first transistor in response to the mirroring current; and
an output node coupled to a source of the transistor and the second current mirror unit, and configured to output a reference voltage,
wherein size of the flipped-gate transistor is less than that of the first transistor;
wherein the flipped-gate transistor and the transistor form a diode pair.