| CPC G05F 3/262 (2013.01) [G05F 1/565 (2013.01); G05F 1/575 (2013.01); G05F 3/26 (2013.01); G05F 3/30 (2013.01)] | 10 Claims |
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1. A self-adaptive low dropout regulator (LDO) circuit, comprising a band gap reference circuit, an error amplifier, a power transistor, a feedback resistor network, and a self-adaptive acceleration response circuit, wherein an output end of the band gap reference circuit is connected with a non-inverting input end of the error amplifier, an inverting input end of the error amplifier is connected with the feedback resistor network, an output of the error amplifier is connected with a gate electrode of the power transistor, the error amplifier and the power transistor are respectively connected with the self-adaptive acceleration response circuit, and a drain electrode of the power transistor is connected with the feedback resistor network;
wherein the self-adaptive acceleration response circuit comprises an acceleration charging circuit, a self-adaptive acceleration charging and discharging circuit, and an acceleration discharging circuit;
wherein:
the non-inverting input end and the inverting input end of the error amplifier are two differential input ends; a gate electrode of a PMOS transistor of a differential pair of the error amplifier is used as the non-inverting input end of the error amplifier to receive a reference voltage, and a drain electrode of the PMOS transistor is connected with a drain electrode of an NMOS transistor, a gate electrode of the NMOS transistor is connected with a first node, which is used as a first output end of the error amplifier corresponding to a reference voltage end of the error amplifier; a gate electrode of another PMOS transistor of the differential pair of the error amplifier is used as the inverting input end of the error amplifier to receive a feedback voltage, and a drain electrode of the another PMOS transistor is connected with a drain electrode of another NMOS transistor, a gate electrode of the another NMOS transistor is connected with a second node, which is used as a second output end of the error amplifier corresponding to a feedback voltage end of the error amplifier; source electrodes of the PMOS transistor and the another PMOS transistor of the differential pair are connected together as a tail current end of the error amplifier;
the acceleration charging circuit is configured to accelerate the charging process of the differential pair of the error amplifier and comprises a first N-channel metal oxide semiconductor (NMOS) transistor, a first P-channel metal oxide semiconductor (PMOS) transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a second NMOS transistor, wherein a gate electrode of the first NMOS transistor is connected with the first node, a drain electrode of the first NMOS transistor is respectively connected with a drain electrode and a gate electrode of the first PMOS transistor, the gate electrode of the first PMOS transistor is connected with a gate electrode of the second PMOS transistor, a drain electrode of the second PMOS transistor is respectively connected with a drain electrode and a gate electrode of the third PMOS transistor and a drain electrode of the second NMOS transistor, the gate electrode of the third PMOS transistor is connected with a gate electrode of the fourth PMOS transistor, a drain electrode of the fourth PMOS transistor is connected with the tail current end of the error amplifier, and a gate electrode of the second NMOS transistor is connected with the second node, source electrodes of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor are connected with a VDD, and source electrodes of the first NMOS transistor and the second NMOS transistor are grounded;
the self-adaptive acceleration charging and discharging circuit is respectively connected with the gate electrode of the power transistor and the tail current end of the differential pair of the error amplifier, to adaptively accelerate both charging and discharging by dynamically balancing a tail current of the tail current end based on load changes; and
the acceleration discharging circuit is respectively connected with the first node, the second node and the gate electrode of the power transistor, to control a discharging speed of a gate voltage of the power transistor.
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