| CPC G04F 10/005 (2013.01) [H03M 1/48 (2013.01); H03M 1/50 (2013.01)] | 19 Claims |

|
1. A digital-to-time converter (DTC), the DTC comprising:
a bias circuit;
a delay circuit operably connected to the bias circuit;
a replica circuit operably connected to the bias circuit, wherein the bias circuit is operable to output a supply signal for the delay circuit and the replica circuit has a negative slope with respect to a signal level of the supply signal and temperature; and
a low dropout voltage regulator (LDO) circuit operably connected between the bias circuit and the delay circuit and the replica circuit.
|