US 12,422,519 B2
Real-time chirp signal frequency linearity measurement
Thomas Bauernfeind, Arbing (AT); Andreas Schwarz, Öpping (AT); Nicolo Guarducci, Linz (AT); Thorsten Brandt, Paphos (CY); Francesco Lombardo, Munich (DE); Bernhard Greslehner-Nimmervoll, Hagenberg (AT); and Daniel Maier, Schenkenfelden (AT)
Assigned to INFINEON TECHNOLOGIES AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Dec. 14, 2022, as Appl. No. 18/066,029.
Application 18/066,029 is a continuation in part of application No. 17/903,238, filed on Sep. 6, 2022, granted, now 12,249,998.
Prior Publication US 2024/0077579 A1, Mar. 7, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G01S 7/35 (2006.01)
CPC G01S 7/352 (2013.01) 20 Claims
OG exemplary drawing
 
1. A radio-frequency integrated circuit (RFIC) comprising:
a phase-locked loop (PLL) configured to generate a frequency modulated signal under control of a control signal;
a frequency divider circuit configured to divide a frequency of the frequency modulated signal to generate a first frequency signal, wherein a frequency of the first frequency signal is proportional to a frequency of the frequency modulated signal; and
a frequency linearity measurement circuit configured to measure a frequency linearity of the frequency modulated signal while the frequency modulated signal is being generated by the PLL, the frequency linearity measurement circuit comprising:
a first measurement circuit comprising a counter, wherein the counter is controlled by a gate signal having a gate signal period, wherein the first measurement circuit is configured to generate a first estimate of an integer number of clock cycles of the first frequency signal within a respective gate signal period of the gate signal;
a second measurement circuit comprising a time-to-digital converter (TDC), wherein the TDC is controlled by the gate signal, and is configured to generate a second estimate of a fractional number of clock cycle of the first frequency signal within the respective gate signal period of the gate signal;
a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period of the gate signal; and
a closed-loop frequency tracking circuit configured to track a frequency error between an expected frequency and a measured frequency, wherein the expected frequency is determined based on the third estimate, and the measured frequency is determined based on a sum of the first estimate and the second estimate.