US 12,422,512 B2
Aging compensation for poly-resistor based current sense amplifier
Ryan Desrosiers, Fort Collins, CO (US)
Assigned to Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed by Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed on Jun. 24, 2022, as Appl. No. 17/849,184.
Prior Publication US 2023/0417854 A1, Dec. 28, 2023
Int. Cl. H02J 7/00 (2006.01); G01R 19/25 (2006.01); G01R 35/00 (2006.01); H02J 50/10 (2016.01); H03F 3/45 (2006.01)
CPC G01R 35/005 (2013.01) [G01R 19/25 (2013.01); H02J 50/10 (2016.02); H03F 3/45475 (2013.01); H03F 2200/462 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first circuit including a first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; wherein the first resistor has a first resistance (Rs); wherein the second resistor and the third resistor each have a second resistance (Rt); wherein the fourth resistor and the fifth resistor each have a third resistance (Rb); wherein the first resistor is configured to carry a first current (Isns) which is based on the first resistance (Rs) and a voltage differential between a first voltage (Vrect) and a second voltage (Vmid); wherein the first amplifier is configured to output a third voltage (Vo) based of the current (Isns); wherein a gain of the first amplifier is based on the second resistance (Rt) and the third resistance (Rb); wherein at least the fourth resistor and the fifth resistor are comprised of a polysilicon material; wherein the third resistance (Rb) increases with aging of the fourth resistor and the fifth resistor;
a second circuit including a sixth resistor comprised of the polysilicon material; wherein the sixth resistor has the third resistance (Rb); wherein the second circuit is configured to output a fourth voltage (Vcal) which is proportional to the third resistance (Rb); and
a processor; wherein the processor is configured to receive one or more digital signals of the third voltage (Vo) and the fourth voltage (Vcal); wherein the processor is configured to determine the current (Isns) based on the third voltage (Vo); wherein the processor is configured to calibrate for the aging of the fourth resistor and the fifth resistor based on the fourth voltage (Vcal) when determining the first current (Isns).